Some thoughts on the uses of schematic capture.

At some point in most circuit designs, a schematic is drawn. There are a number of uses for this diagram.

One is to create a visual representation of the circuit that simplifies the task of the electronic engineer to check for connectivity and component choices and from which an electrical parts list can be generated.

Another is to capture the circuit design in a format that not only allows the necessary electrical information about the components to be attached to it but also sufficient mechanical information so that a netlist can be generated from this schematic which can then inform a PCB layout package of the physical packaging and pinout of each component.

This aspect of the use of the schematic is extended when layout for Signal Integrity, RF and Microwave is considered. Then, physical constraints such as trace impedances, propagation delays and crosstalk considerations must be included as part of the schematic before it can safely be passed into PCB layout.

A third use for the schematic is to attach information about simulation models to it so that the circuit being designed can be simulated. This will include electrical models of the active and passive components. For Signal Integrity, RF and Microwave it will also include models for the device packages, connectors and the nets between them as well as the substrate material on which the PCB is to be built.

The first two uses of the schematic can be considered as being inert or inactive. For simulation purposes, the circuit being represented is active. Hence additional components are required that are not normally part of an inert schematic. Sources must be added to provide power and to stimulate the circuit. Loads may also be required. Voltage, current and power probes may also need to be added around it, especially if these have to provide defined loading and bandwidths so that simulation waveform plots are representative of what would be seen when probing a real circuit with realistic test equipment. Directives must be added to control what simulations are to be run and to provide any parameters that may be needed by components or the operating environment. Other directives may be added to post-process the results of a simulation perhaps for use in later runs.

One way to achieve this would be to treat the schematic as a hierarchical block and then put the necessary power supplies, signal sources loads and directives around it in the form of a test jig.

However, this may not be a very efficient way to simulate a circuit particularly if it is large and complex. Such an approach may generate huge output data files and run slowly. More importantly, the simulation may fail to converge. Even with help from user friendly error messages from the simulator, debugging convergence failures in a large circuit can be very time consuming simply because they may occur in a part of the circuit that may seem completely unintuitive.

A more efficient use of simulation may be to simplify, using behavioural models, parts of the circuit whose function is not critical to the section to be studied or even to strip out unnecessary regions of the circuit. Breaking the circuit up into functional stages or blocks and simulating each in turn, using the output from one as the input to the next is another way to simplify and so speed up the task of simulation.

Once these sorts of techniques have been applied, the active simulation schematic may appear very different from the inert schematic from which it has been derived. In fact there may be several simulation schematics each covering a different part of the overall circuit or studying some particular aspect of its behaviour or performance.

So far this discussion has assumed that simulation takes place later in the design process. In effect, after schematic capture. If simulation is included right from the start of a design, the simulation schematic - or more likely, schematics - may start life looking much like a simulation schematic that has been condensed out of the inert schematic. However, being driven from a largely simulation point of view, it may not contain as much non-simulation related component information as its' inert cousin.

This creates the problem that a pure simulation schematic is not really suitable for use in parts list and PCB generation. Non-simulation related components and information can be added to a simulation schematic but may require extra work to define new symbols and to carefully check pin number mappings from components and subcircuits onto physical packages to be used on the PCB layout.

This may not be too onerous a task if the schematic capture tool used to generate the simulation schematic is one of those intended primarily for the first two uses described above but there are several simulation tools that come with their own schematic capture front ends, not all of which provide all the features and functions of a more general schematic capture tool. Whilst they can all generate a SPICE - or equivalent - netlist, this does not contain much, if any, of the additional information required for PCB generation. Some simulations tools can export a netlist in a format that can be read by a PCB layout package but the user may have to jump through a few hoops in order to build components and symbols that are correctly formatted in a SPICE netlist and also pass on the relevant information to - and are formatted correctly in - the PCB layout tool netlist.

One example is a connector. In a simple simulation, this does not even have to be shown. It is essential for the PCB layout. In the simulation it may have no effect, it is just another piece of the same net. For PCB layout it has to have pin numbers, package information and the physical orientation of the male and female halves must be accounted for. It possible to build a component or sometimes just a symbol in a simulation schematic capture tool that will fulfil these needs but how to do so may not be well documented simply because these may not be seen as the usual requirements of such a tool.

This situation changes somewhat if design for Signal Integrity, RF and Microwave simulation is to be included. In these situations, effectively everything in the schematic is a component and so affects electrical performance. Nets, vias, connectors, test pins, substrate material and layer stack-up etc., etc. all affect circuit behaviour and so must be modelled. In tools that are designed for this level of simulation, the additional information required for parts list and PCB generation are often already there. In some of the high end tools the schematic - including simulation models and pre-layout constraint data - and the PCB layout including simulation models modified by post-layout constraints are essentially the same object and can be edited interchangeably.

Another aspect of having inert and simulation schematics is that in some types of simulation, such as switch mode power supply design, there are linearisation techniques that can reduce simulation times by between 100 and 10,000 times whilst giving results that for all practical purposes are identical to a full switching simulation of the same circuit. Clearly the simulation schematic for a linearised model may look very different from the switching version. For example applying such techniques to a SEPIC power supply requires a topological transformation that moves the coupling capacitor way off where it is in the switching topology.

Perhaps the biggest problem in having separate inert and simulation schematics is that of synchronising the two. It is not clear how or indeed when design changes in one should update the other, in either direction. An automatic updating process may seem less error prone than a manual procedure but given what may be significant difference between the two types of schematics, it is by no means clear how it could be achieved safely and reliably.